Many electronics manufacturers routinely test circuit boards using the Boundary-Scan Test technique set forth in the IEEE 1149.1 Standard described in the IEEE publication Test Access Port (TAP) and Boundary Scan Architecture (hereinafter incorporated by reference). For Boundary-Scan Testing to occur, each circuit board must have a Boundary-Scan Test architecture. In particular, each board must possess at least one, and preferably, a plurality devices that each include one or more Boundary-Scan cells coupled in a serial chain for storing values associated with the operation of that device. In addition, each Boundary-Scan device must posses a Test Access Port (TAP) controller whose architecture is described in the above-described IEEE publication.
Each TAP controller manages the testing process for its associated device in accordance with a Test Mode Select (TMS) signal and Test Clock (TCK) signals provided from an external test system. At the outset of testing, each TAP controller shifts, via its Test Data Input (TDI) a swing of test bits into the chain of Boundary-Scan cells and then apply the string. When the circuit board is operating properly, the logic values latched in the Boundary-Scan cells assume prescribed values. If there are faults in the circuit board, then the logic values latched in one or more Boundary-Scan cells will differ from their corresponding prescribed values. To detect such differences, the external test system shifts out the bits from the Boundary-Scan cells for comparison to a set of pre-computed values for a fault-free board. Any differences between the shifted-out bits and the pre-computed values represent possible faults in the circuit board.
In the past, Boundary-Scan testing has required an individual test controller for managing the testing of an associated board. Presently, several manufacturers have developed slave modules for connecting individual circuit boards to a single system test controller (i.e., a test master) by way of a Boundary-Scan test bus that has separate TDI, TMS, TDO and TCK lines in accordance with the IEEE 1149.1 Standard. For this reason, the Boundary-Scan test bus will hereinafter be referred to as an 1149.1 backplane test bus. To accomplish Boundary-Sean testing in this manner, the test master first selects an individual board for testing by placing the address of that board on the 1149.1 backplane test bus. The board having the corresponding address responds to the test master, whereupon the test master supplies test information to, and receives test responses from, the corresponding board using the IEEE 1149.1 protocol.
The above-described networked approach to Boundary-Scan testing suffers from the disadvantage of possessing no mechanism for detecting transmission errors. In practice, the backplane test bus carrying signals from the test master to the individual boards may suffer from electrical noise that can cause errors in the transmitted information. Such transmission errors may not only adversely affect the test results, but may damage the one or more devices within the network
Thus, there is a need for a technique for detecting transmission errors on the 1149.1 backplane test bus in a networked system.